ppc4xx: (Re-)Enable CONFIG_PCI_PNP on AMCC 440EPx Sequoia

The 440EPx has a problem when the PCI_CACHE_LINE_SIZE register is
set to non-zero, because it doesn't support MRM (memory-read-
multiple) correctly. We now added the possibility to configure
this register in the board config file, so that the default value
of 8 can be overridden.

Here the details of this patch:

o drivers_pci_auto.c: introduce CFG_PCI_CACHE_LINE_SIZE to allow
  board-specific settings. As an example the sequoia board requires 0.
  Idea from Stefan Roese <[email protected]>.
o board/amcc/sequoia/init.S: add a TLB mapping at 0xE8000000 for the
  PCI IO-space. Obtained from Stefan Roese <[email protected]>.
o include/configs/sequoia.h: turn CONFIG_PCI_PNP back on and set
  CFG_PCI_CACHE_LINE_SIZE to 0.

Signed-off-by: Gary Jennejohn <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>

diff --git a/board/amcc/sequoia/init.S b/board/amcc/sequoia/init.S
index 45bcd4bef759ab385d745ff0120aaebca7b54abb..5fe3af9a092a2ed7b12c0224044840d2e9407fe2 100644 (file)
--- a/board/amcc/sequoia/init.S
+++ b/board/amcc/sequoia/init.S
@@ -126,6 +126,9 @@ tlbtab:
        /* TLB-entry for peripherals */
        tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
 
+       /* TLB-entry PCI IO Space - from [email protected] */
+       tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
+
        tlbtab_end
 
 #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)

diff --git a/drivers/pci_auto.c b/drivers/pci_auto.c
index 2378553be5acf75fe3992301e2fb43390e96a5ff..acfda83ba50b325f0f2076c8e9544796f8629d91 100644 (file)
--- a/drivers/pci_auto.c
+++ b/drivers/pci_auto.c
@@ -28,6 +28,11 @@
 
 #define        PCIAUTO_IDE_MODE_MASK           0x05
 
+/* the user can define CFG_PCI_CACHE_LINE_SIZE to avoid problems */
+#ifndef CFG_PCI_CACHE_LINE_SIZE
+#define CFG_PCI_CACHE_LINE_SIZE        8
+#endif
+
 /*
  *
  */
@@ -150,7 +155,8 @@ void pciauto_setup_device(struct pci_controller *hose,
        }
 
        pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat);
-       pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
+       pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE,
+               CFG_PCI_CACHE_LINE_SIZE);
        pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
 }
 

diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h
index 824a81240cdc949d41910858ae094c106db8321a..c2e1386217f9dcda7f28ea8162ba0da016316062 100644 (file)
--- a/include/configs/sequoia.h
+++ b/include/configs/sequoia.h
@@ -400,7 +400,8 @@
  *----------------------------------------------------------------------*/
 /* General PCI */
 #define CONFIG_PCI                     /* include pci support          */
-#undef CONFIG_PCI_PNP                  /* do (not) pci plug-and-play   */
+#define CONFIG_PCI_PNP                 /* do pci plug-and-play   */
+#define CFG_PCI_CACHE_LINE_SIZE        0 /* to avoid problems with PNP */
 #define CONFIG_PCI_SCAN_SHOW           /* show pci devices on startup  */
 #define CFG_PCI_TARGBASE        0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/